Semiconductor chip having bond pads

ABSTRACT

A semiconductor package includes a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern, The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. patent application Ser. No. 11/556,153, filed on Nov. 2, 2006, now pending, which is a Continuation of U.S. patent application Ser. No. 10/651,813, filed on Aug. 28, 2003, now issued U.S. Pat. No. 7,148,578, which is a Divisional of U.S. patent application Ser. No. 10/192,800, filed on Jul. 9, 2002, now issued U.S. Pat. No. 6,642,627, which claims priority from Korean Patent Application Nos. 2001-0041154, filed on Jul. 10, 2001, and 2002-0003030, filed on Jan. 18, 2002, all of which are herein incorporated by reference in their entirety.

BACKGROUND

1. Field of the Invention

The present invention relates generally to semiconductor devices and, more particularly, to a semiconductor chip having bond pads and to a semiconductor package.

2. Description of the Related Art

The industry is expending significant effort toward forming smaller and thinner chips to meet the demand for high packing density in high-speed, multi-functional semiconductor devices. To reduce chip size, the size of bond pads as well as the pitch between bond pads should be reduced.

Conventional semiconductor chips have either a center pad-type or a peripheral pad-type structure. FIG. 1 is a plan view of a conventional center pad-type semiconductor chip. FIG. 2 is a cross-sectional view of the conventional center pad-type chip taken along line 2-2 of FIG. 1. FIG. 3 is a plan view of a conventional peripheral pad-type semiconductor chip. FIG. 4 is a cross-sectional view of the conventional peripheral pad-type chip taken along the line 4-4 of FIG. 3.

Referring to FIGS. 1 and 2, a center pad-type semiconductor chip 110 comprises a peripheral circuit region A_(peri) for forming bond pads 112 and cell regions A_(cell1) and A_(cell2). The peripheral circuit region A_(peri) is formed in the center region of a semiconductor substrate 111. The cell regions A_(cell1) and A_(cell2) are formed on the sides of the peripheral circuit region A_(peri).

Referring to FIGS. 3 and 4, a peripheral pad-type semiconductor chip 120 comprises peripheral circuit regions A_(peri1) and A_(peri2) and a cell region A_(cell). The cell region A_(cell) is formed in the center region of the semiconductor substrate 121. The peripheral circuit regions A_(peri1) and A_(peri2) are formed on the sides of the cell region A_(cell). Referring to FIGS. 2 and 4, a passivation layer 113, 123 is formed over the cell regions and the peripheral circuit regions in both the center and peripheral pad-type chips.

In the conventional semiconductor chips 110, 120 of FIGS. 1 through 4, an additional chip area is needed in peripheral circuit regions for forming bond pads 112, 122. As a result, the ability to reduce the size of the conventional semiconductor chips 110 and 120 is limited in both chip pad types.

Furthermore, it has been difficult to reduce the bond pad size and the pitch between the bond pads 112, 122 in the conventional semiconductor chips 110 and 120. This is because the bond pads 112, 122 must have a designed minimum size and pitch for electric die sorting (EDS) and to form electrical interconnections.

The ability to reduce the size of a multi-chip package (MCP) including multiple conventional semiconductor chips in a single body package is also limited due to problems such as the difficulty of stacking center pad-type chips on chips of the same or similar types. That is, wire bonding can be complicated and difficult due to long loop wires in such cases.

Accordingly, there is a need for a smaller semiconductor chip that can easily form an MCP without suffering from the problems mentioned above.

SUMMARY

In one embodiment, a semiconductor package comprises a package substrate including a surface having a plurality of bonding tips formed thereon; and at least one semiconductor chip mounted on the package substrate surface. The semiconductor chip comprises a semiconductor substrate having at least two surfaces, wherein at least one of the surfaces includes a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed over at least a portion of the peripheral circuit region of the semiconductor substrate; a pad-rearrangement pattern electrically connected to the bond pad-wiring pattern, the pad-rearrangement pattern including at least one bond pad disposed over at least a part of the cell region; and an insulating layer formed on the pad-rearrangement pattern, the insulating layer having at least one opening to expose the at least one bond pad through the formed insulating layer, wherein each bonding tip is electrically connected to a corresponding bond pad.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages of the present invention will be more readily understood through the following detailed description provided with reference to the accompanying figures, wherein like reference numerals designate like structural elements, and, in which:

FIG. 1 is a plan view of a conventional center pad-type semiconductor chip;

FIG. 2 is a cross-sectional view of the conventional center pad-type taken along the line 2-2 of FIG. 1;

FIG. 3 is a plan view of a conventional peripheral pad-type semiconductor chip;

FIG. 4 is a cross-sectional view of the peripheral pad-type chip taken along the line 4-4 of FIG. 3;

FIGS. 5 to 8 are cross-sectional views of a semiconductor chip illustrating a process of manufacturing a semiconductor chip according to an embodiment of the present invention;

FIG. 9 is a plan view of the semiconductor chip shown in FIG. 8;

FIG. 10 is an enlarged cross-sectional view of a semiconductor chip illustrating an alternative configuration of portion A of FIG. 8;

FIG. 11 is a cross-sectional view of the semiconductor chip of FIG. 9, following wire bonding;

FIG. 12 is a cross-sectional view illustrating a semiconductor chip according to another embodiment of the present invention;

FIGS. 13 to 15 are cross-sectional views of a semiconductor chip illustrating a process of manufacturing a semiconductor chip according to yet another embodiment of the present invention;

FIG. 16 is a cross-sectional view of a semiconductor chip according to a further embodiment of the present invention;

FIG. 17 is a cross-sectional view of a semiconductor chip according to a still further embodiment of the present invention;

FIG. 18 is a cross-sectional view of an MCP according to another embodiment of the present invention;

FIG. 19 is a cross-sectional view of an MCP according to another embodiment of the present invention,

FIG. 20 is a cross-sectional view of an MCP according to yet another embodiment of the present invention;

FIG. 21 is a cross-sectional view of an MCP according to a further embodiment of the present invention;

FIG. 22 is a cross-sectional view of an MCP according to a still further embodiment of the present invention; and

FIG. 23 is a cross-sectional view of an MCP according to a still further embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 8 is a cross-sectional view of a semiconductor clip 10 constructed according to an embodiment of the present invention. Referring to FIG. 8, a semiconductor chip 10 comprises a semiconductor substrate 11 having integrated circuits formed thereon. In particular, the semiconductor substrate 11 includes a peripheral circuit region A_(peri) formed in the center region thereof and cell regions A_(cell1) and A_(cell2) arranged on the sides of the peripheral circuit region A_(peri). A bond pad-wiring pattern 12 is formed in a predetermined area of the substrate 11. The bond pad-wiring pattern 12 can be made of a metal having excellent electrical conductivity, such as aluminum (Al).

The bond pad-wiring pattern 12 is preferably formed in a center region of the semiconductor substrate 11. One end of the bond pad-wiring pattern 12 is preferably formed on the portion of the peripheral circuit region A_(peri). In the conventional semiconductor chip, an additional chip area is needed in peripheral circuit regions for forming bond pads having a minimum size and pitch designed for electric die sorting (EDS) and making electrical interconnections. According to the forgoing embodiment of the present invention, however, no larger additional area for forming bond pads is required, rather only the small portion of the bond pad-wiring pattern 12 needs to be formed on the peripheral circuit region A_(peri). The remaining portion of the bond pad-wiring pattern 12 extends across a portion of the cell region according to an embodiment of the present invention. The width of the semiconductor substrate 11 can therefore be reduced by approximately the width of the bond pad area of the conventional semiconductor chip.

According to another aspect of the present invention, as shown in FIG. 16, the bond pad-wiring pattern 12 can alternatively be formed entirely within the peripheral circuit region. Also, the bond pad-wiring pattern 12 can be formed entirely within the cell region (although not shown). In these cases, the size of the bond pad-wiring pattern 12 can be made small because a designed minimum size and pitch for electric die sorting (EDS) and electrical interconnections is not needed.

Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced using the above-described principles of the present invention as explained above and further below.

A passivation layer 16 is formed on the bond pad-wiring pattern 12. An interlayer dielectric (ILD) 13 is then formed on the passivation layer 16. The ILD 13 is made of a material having good insulation and integration properties to protect bond pads 17 from mechanical stress due to subsequent wire bonding, beam lead bonding, or ball bonding. For example, a high-density plasma (HDP) oxidized layer, a benzocyclobutene (BCB) layer, a polybenzoxazole (PBO) layer, or a polyimide layer may be used as the ILD 13. An HDP oxide layer using silan, oxygen and argon gases, for example, an HDP-SiO₂ layer is preferably used. The passivation layer 16 and the ILD 13 have openings 14 formed therein to expose predetermined portions of the bond pad-wiring pattern 12 a.

A pad-rearrangement pattern 15, having a predetermined layout, is formed on the ILD 13. As shown in portion “A” of FIG. 8, the openings 14 are filled with the pad-rearrangement pattern 15. An alternative configuration of portion A of FIG. 8 is illustrated in FIG. 10. The pad-rearrangement pattern 15 preferably comprises three layers. These three layers can, for example, include a titanium (Ti) layer having a thickness of about 300 to 500 Å, an aluminum (Al) layer having a thickness of about 15,000 Å, and a titanium nitride (TiN) layer having a thickness of about 300 to 500 Å. The pad-rearrangement pattern 15 may be formed of copper (Cu), aluminum (Al), zinc (Zn), iron (Fe), platinum (Pt), cobalt (Co), lead (Pb), nickel (Ni), or an alloy of these elements.

An insulating layer 18 is formed on the pad-rearrangement pattern 15. The insulating layer 18 may be an HDP oxide layer such as an HDP-SiO₂ layer or an HDP-SiN layer. The insulating layer 18 may further comprise a polyimide layer on the HDP-SiO₂ layer so as to protect integrated circuits from alpha particles. A predetermined portion of the pad-rearrangement pattern 15 is exposed through the insulating layer to define the bond pads 17. The bond pads 17 are preferably flush with the pad-rearrangement pattern 15. The bond pads 17 are disposed above at least part of the cell regions A_(cell1), A_(cell2) of the substrate 11. Although the bond pads 17 shown in FIG. 9 are disposed in a single row along opposing edges of the substrate 11, the pads 17 may be disposed along all four edges or in a zigzag shape.

According to one embodiment, the pad-rearrangement pattern 15 reroutes the bond pads 17 from the bond pad-wiring pattern 12 in the peripheral circuit region A_(peri) to above the cell regions A_(cell1) and A_(cell2). As shown above, one end of the pad-rearrangement pattern 15 is electrically connected to the exposed bond pad-wiring pattern 12 via openings 14. The other end extends toward the edge of the substrate 11. In other words, according to one aspect of the present invention, the portion of the pad-rearrangement pattern 12 extends substantially from the center region of the semiconductor substrate 11 toward an edge of the semiconductor substrate 11. The bond pads 17 can therefore be formed along sides of the semiconductor substrate 11. Thus, according to various embodiments of the present invention, peripheral pad type semiconductor chips can be fabricated using center pad type semiconductor chips, which are known to have improved electrical performance characteristics over the peripheral pad type chips. The pitch between the bond pads can increase. During the EDS test, a probe can easily contact the bond pads. These modified peripheral pad chips thus need not be packaged in a lead-on-chip (LOC) type package, but may be implemented in a conventional package.

Referring to FIG. 11, electrical connection means such as bonding wires 99 are coupled to the bond pads 17. If necessary, the positions of bond pads 17 can be adjusted depending on the design and structure of the electrical interconnections.

As described above, the bond pads 17 of this embodiment are preferably formed over at least a part of the cell regions of the substrate 11. Therefore, the peripheral circuit region A_(peri) has a much smaller width than that of the conventional peripheral circuit region. Thus, the total width of the semiconductor chip 10 can be reduced. The widths of the cell regions A_(cell) ¹ and A_(cell2) may be the same as that of the conventional cell region. Of course, the total thickness of the semiconductor chip 10 increases due to the formation of the pad-rearrangement pattern 15 and the insulating layer 18 above the cell regions A_(cell1) or A_(cell2). The increased percentage in total thickness of the chip 10 is no more than the reduced percentage of the total width of the chip 10. The total size of the chip 10 can be therefore reduced.

A method of manufacturing the above-described semiconductor chip 10 will now be described. Referring to FIG. 5, a semiconductor substrate 11 includes on-chip circuits formed on the cell regions A_(cell1), A_(cell2) and the peripheral circuit region A_(peri). If the semiconductor chip 10 is a memory device, the circuits formed on the cell regions A_(cell1), A_(cell2) are memory cells having MOS transistors and capacitors, while the circuits formed on the peripheral circuit region include, for example, address decoding circuits and data input/output buffers for the memory cells. The bond pad-wiring pattern 12 is formed on the substrate 11 to be selectively connected to the integrated circuits. The passivation layer 16 is then formed on the bond pad-wiring pattern 12. The bond pad-wiring pattern 12 is formed in a predetermined layout using conventional techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) including sputtering. As described above, although the bond pad-wiring pattern 12 can be formed on both the cell regions A_(cell1), A_(cell2) and the peripheral circuit region A_(peri), the bond pad-wiring pattern may be formed just the cell regions A_(cell1), A_(cell2) (not shown).

Next, as shown in FIG. 6, the ILD 13 is formed on the passivation layer 16. Openings 14 are formed extending through the passivation layer 16 and the ILD 13 to expose predetermined portions of the bond pad-wiring pattern 12. The ILD 13 is made of a material such as HDP-SiO₂ having good integration and insulating qualities. The integrated circuits under the ILD 13 can therefore be protected from physical stresses during the formation of electrical interconnections. The ILD 13 also helps planarize the underlying structure. The openings 14 can be formed above either the cell regions A_(cell1), A_(cell2) or the peripheral circuit region A_(peri).

Although the forgoing embodiment comprises a single ILD, the present invention may comprise two or more ILDs, as shown in FIG. 12 and FIG. 17. Referring to FIGS. 12 and 17, second ILDs 20 a, 20 can be interposed between the ILD 13 and the pad-rearrangement pattern 15. In particular, as illustrated in FIGS. 12 and 17, because the second ILDs 20 a, 20 are interposed between the ILD 13 and the pad-rearrangement pattern 15, the electrical properties of the semiconductor chips 30, 90 are improved. The capacitance, for example, can be lowered. The thickness of the second ILD 20 a is between 2 to 50 μm, for example determined base on the capacitance and the intensity supplement. The second ILD 20 a may be made of benzocyclobutene (BCB), polybenzoxazole (PBO), polyimide, and so on. Also, in this case, the planarization process is preferably performed on the ILDs to improve the planarity of the ILDs 13, 20 a or 20. Accordingly, the planarity of the pad-rearrangement pattern 15 thereon can be in turn improved. Further, connection failures of the bonding wires or the beam leads on the bond pads 17 are prevented and the adhesion therebetween are improved. The planarization is preferably accomplished through chemical and mechanical polishing (CMP).

According to one aspect of the present invention, the ILDs 13 and 20 of the semiconductor chip 90 (FIG. 17) distribute mechanical stresses during the formation of the electrical interconnections and protect the bond pads 17 from the mechanical stresses. In addition, since the bond pads 17 are formed after two planarization processes on the two ILDs, the bonding stability of the wire bonding between the bond pads 17 and the external device is improved.

Referring to FIG. 7, the pad-rearrangement pattern 15 is formed on the ILD 13. The pad-rearrangement pattern 15 fills the openings 14 and is electrically connected to the bond pad-wiring pattern 12. The pad-rearrangement pattern 15 is obtained in a desired layout using CVD or sputtering, for example.

Referring to FIG. 8, an insulating layer 18 is formed on the pad-rearrangement pattern 15 and includes an opening 19 to expose predetermined portions of the pad-rearrangement pattern 15. The exposed portions of the pattern 15 are defined as the bond pads 17. The insulating layer 18 is preferably made of HDP-SiO₂ to protect the integrated circuits from mechanical stresses. The insulating layer 18 may further comprise a polyimide layer on the HDP-SiO₂ layer to protect the integrated circuits from alpha particles. The ILD 20 a and the insulating layer 18 can alternatively made of polyimide.

FIGS. 13 through 15 are cross-sectional views of a semiconductor chip illustrating a process of manufacturing a semiconductor chip in accordance with another embodiment of the present invention. In this embodiment, as shown in FIG. 15, a semiconductor chip 50 comprises a second ILD 20 b on a first ILD 13. Bond pads 17 of this embodiment, however, are formed on the first ILD 13. In order to prevent a cushioning effect due to the mechanical stress of the electrical interconnections, portions of the second ILD 20 b under the bond pads 17 are removed.

In particular, Referring to FIGS. 13 through 15, a semiconductor substrate 11 includes a bond pad-wiring pattern 12 preferably formed on at least a portion of the peripheral circuit region A_(peri) and electrically connected thereto. A passivation layer 16 is formed on the semiconductor substrate 11 and on the bond pad-wiring pattern 12. The first ILD 13 is formed over the semiconductor substrate 11 including the bond pad-wiring pattern 12. A second ILD 20 b is then formed over the first ILD 13. A first opening 22 is formed through the first and second ILDs 13, 20 b and the passivation layer 16 to expose a portion of the bond pad-wiring pattern 12. A second opening 24 is formed through the second ILD 20 b to expose a portion of the first ILD 13. A pad-rearrangement pattern 15 is formed over the second ILD 20 b and within the first opening 22 and is electrically connected to the bond pad-wiring pattern 12. The pad-rearrangement pattern 15 is also formed within the second opening 24. An insulating layer 18 is formed over the pad-rearrangement pattern 15 and includes an opening 26 therein that exposes a portion of the pad-rearrangement pattern 15 formed within the second opening 24 to define the bond pads 17 over at least a part of the cell region A_(cell). The portions of the pad-rearrangement pattern 15 not covered by the insulating layer 18 provide the bond pads 17. This embodiment has the similar features as described previously. For example, the bond pad-wiring pattern 12 is formed substantially in a center region of the semiconductor substrate 11.

Various MCPs utilizing the semiconductor chips according to the embodiments of the present invention are obtainable, which will be explained below. Referring to FIG. 18, an MCP 200 preferably comprises a first chip 210 a and a second chip 210 b that are vertically stacked on a package substrate 251. A printed circuit board (PCB) or tape wiring substrate can be used as the package substrate 251. The substrate surface preferably has a plurality of bonding tips 253 formed thereon. The first and second chips 210 a and 210 b are preferably the same type of chips. The first and second chips 210 a and 210 b can have structures formed in accordance with the principles of the present invention described previously. For example, a bond pad-wiring pattern can be formed substantially in a center region of a semiconductor substrate, for example. Accordingly, the bond pads 217 a and 217 b of the first and second chips 210 a and 210 b are formed over cell regions along sides of the chips 210 a and 210 b. Thus, the chips 210 a and 210 b can have a modified configuration, i.e., a center pad-type chip can be modified into a peripheral pad-typed chip.

The first and second chips 210 a and 210 b are electrically connected to the package substrate 251 by electrical connection means such as bonding wires 257, which are in turn electrically connected to the bonding tips 253. Thus, each bonding tip 253 is electrically connected to a corresponding one of the bond pads 271 a, 271 b.

The first chip 210 a is mounted on the package substrate 251 with an adhesive 261, and the second chip 210 b is mounted on the first chip 210 a with an adhesive material 263. The adhesive material 263 is interposed between the first and second chips 210 a and 210 b, thus ensuring enough space for the bonding wires 257 used in connecting the first chip 210 a with the package substrate 251.

An encapsulant 259, formed of a material such as an epoxy molding compound, protects the upper surface of the package substrate 251 from an external environment by encapsulating the first and second chips 210 a, 210 b and the bonding wires 257. Solder balls 271 are formed on the lower surface of the package substrate 251 to provide external connection terminals.

As described above, since the MCP 200 according to this embodiment includes multiple semiconductor chips in a single package body, the principles of the present invention can be used to increase memory capacity as well as the number of input/output pins without complicated assembly processes.

Referring to FIG. 19, an MCP 300 according to another embodiment of the present invention comprises a first chip 310 a and a second chip 310 b mounted side by side on a package substrate 351. Here, the first and second chips 310 a, 310 b preferably have structures the same as or similar to the structures described in FIG. 21 or the same as or similar to structures of the chip embodiments described above. For example, the first and second chips 310 a, 310 b are preferably electrically connected to the substrate 351 by bonding wires 357 through bonding tips 353. Reference numerals 359, 361, 371 are used herein to denote an encapsulant, adhesives, and solder balls, respectively.

Referring now to FIG. 20, an MCP 400 according to yet another embodiment of the present invention comprises three semiconductor chips 410 a, 410 b, 410 c that are stacked sequentially on a package substrate 451. The chips 410 a, 410 b, 417 c preferably have structures similar to structures described previously in accordance with the principles of the present invention. For example, the semiconductor chips 410 a, 410 b, 410 c are preferably peripheral pad-type chips having realignment bond pads 417 a, 417 b, 417 c formed over cell regions along a periphery (or sides) thereof. The semiconductor chips 410 a, 410 b, 410 c can have different widths from each other. For example, the semiconductor chips 410 a, 410 b, 410 c are preferably stacked in order of size, i.e., from the largest chip 410 a to the smallest chip 410 c. Different configurations are possible, however, depending on applications. For example, any two of the chips 410 a, 410 b, 410 c may have the same width.

The semiconductor chips 410 a, 410 b, 410 c are preferably electrically connected to the substrate 451 by bonding wires 457 through bonding tips 453. As described above, the MCP 400 of this embodiment can comprise different types of chips. Since the center pad-type chip is modified into a peripheral pad-type chip, it is possible to vertically stack the multiple chips and the lengths of the bonding wires can be made shorter to allow easier wire bonding.

Turning to FIG. 21, an MCP 500 according to yet another embodiment of this invention is a dual die package (DDP) comprising first and second semiconductor chips 510 a, 510 b. A lead frame 551 is used to mount the chips 510 a, 510 b. The second semiconductor chip 510 b is preferably formed in accordance with the principles of the present invention described above. For example, the second semiconductor chip 510 b can be a peripheral pad-type chip having a realignment bond pad 517 b formed on the peripheral circuit region along sides of the chips 510 a, 510 b. In contrast, the first semiconductor chip 510 a preferably has a center pad-type bond pad 517 a.

The MCP 500 of this embodiment does not include die pads for mounting the semiconductor chips 510 a, 510 b. Instead, the leads of the lead-frame 551 employed in the LOC type package are preferably used. The length of the leads of the lead frame 551 is preferably longer than that of the conventional leads, but this is not required. The upper surface of the first semiconductor chip 510 a is attached to lower surfaces of opposing leads of the lead frame 551 by adhesive tape 563. The bond pad 517 a of the first chip 510 a is disposed between the opposing leads of the lead frame 551 and is wire-bonded to the upper surface of the corresponding leads of the lead frame 551 by bonding wires 557 a. The upper surface of the second chip 510 b is attached to the lower surface of the first chip 510 a with an adhesive 561. The realignment bond pad 517 b of the second chip 510 b is wire-bonded to the lower surface of the corresponding leads of the lead frame 551 by bonding wires 557 b. The first and second chips 510 a, 510 b and corresponding bonding wires 557 a, 557 b are encapsulated by an encapsulant 559.

In summary, the MCP 500 is a DDP comprising semiconductor chips modified from a center pad-type into a peripheral pad-type or vice versa. In addition, with the MCP 500, larger semiconductor chips can be used as compared to the other embodiments described previously.

Referring to FIG. 22, an MCP 600 according to a still further embodiment of the invention is a DDP comprising first and second semiconductor chips 610 a, 610 b. A die pad 653 and leads 651 are used for mounting the chips 610 a, 610 b. The first and second chips 610 a, 610 b are preferably a peripheral pad-type where bond pads 617 a, 617 b are formed along sides of the chips 610 a, 610 b. The first and second chips 610 a, 610 b are attached to the upper and lower surfaces, respectively, of the die pad 653 with an adhesive 661. The bond pads 617 a of the first chip 610 a are wire-bonded to the upper surfaces of the leads 651 by bonding wires 657 a. The bond pads 617 b of the second chip 610 b are wire-bonded to the lower surfaces of the leads 651 by bonding wires 657 b. The first and second chips 610 a, 610 b and bonding wires 657 a, 657 b are encapsulated by an encapsulant 659.

The MCP 600 of this embodiment comprises chips formed in accordance with the previously-described principles of the present invention. For example, the MCP 600 can comprise semiconductor chips modified from a center pad-type into a peripheral pad-type.

Referring to FIG. 23, an MCP 700 according to a further embodiment of the present invention includes four semiconductor chips 710 a, 710 b, 710 c, 710 d. Preferably, a width of a first chip 710 a is substantially greater than a width of a second chip 710 b. Also, a width of a third chip 710 c is preferably substantially greater than a width of a fourth chip 710 d. The width of the first chip 710 a is also preferably approximately equal to the width of the third chip 710 c. A person skilled in the art will appreciate, however, that the widths of the first and third chips 710 a, 710 c, or the second and fourth chips 710 b, 710 d need not necessarily be equal, but may be made different depending on a desired application.

A lead frame 751 having a die pad 753 is used to mount the chips 710 a, 710 b, 710 c, 710 d. The non-active surface of the first chip 710 a is attached to the upper surface of the die pad 753. The non-active surface of the second chip 710 b is attached to a portion of the active surface of the first chip 710 a. The non-active surface of the third chip 710 c is attached to the lower surface of the die pad 753. The non-active surface of the fourth chip 710 d is attached to a portion of the active surface of the third chip 710 c. The first and second chips 710 a, 710 b preferably face upwardly and the third and fourth chips 710 c, 710 d preferably face downwardly.

The bond pads 717 a, 717 b of the first and second chips 710 a, 710 b are wire-bonded to the upper surface of the lead of the lead frame 751 through first and second bonding wires 757 a, 757 b, respectively. The bond pads 717 c, 717 d of the third and fourth chips 710 c, 710 d are wire-bonded to the lower surface of the lead of the lead frame 751 by third and fourth bonding wires 757 c, 757 d, respectively. The semiconductor chips 710 a, 710 b, 710 c, 710 d and bonding wires 757 a, 757 b, 757 c, 757 d are encapsulated with an encapsulant 753. Herein, the reference numerals 761, 762, 763, and 764 each represent an adhesive.

In various embodiments of the present invention, such as those described previously, electrical connections between the chips and the lead frame or package substrate are preferably made by wire bonding. Other techniques may be used instead, however, to form an MCP according to the present invention.

Also, a person skilled in the art will appreciate that other types of lead frames or tape can be used different from the lead frames illustrated in the accompanying figures. For example, the lead frames have inner leads bent twice and outer leads are J-leaded. In this case, the bent portion of the inner leads overlies on the active surface of one of plural chips and attached thereto by an adhesive tape or other suitable adhesives.

Although the MCPs of the various preferred embodiments of the present invention are illustrated as including between two and four semiconductor chips in a single MCP body, other numbers of chips can be incorporated in an MCP depending on the desired application.

The chips can be all the same type of chip, such as memory chips, for example. As another example, one of the chips can be a DRAM and the other can a flash memory. Alternatively, the chips can be of different types. For example, one of the chips can be a memory chip such as a flash memory, a static random access memory (SRAM), or a dynamic random access memory (DRAM), and another chip can be a non-memory chip such as a microprocessor. The present invention can therefore be used to implement a system in a package (SIP) and thereby significantly increase packing density.

Although various preferred embodiments of the present invention have been disclosed herein for illustrative purposes, those skilled in the art will appreciate that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the invention as provided in the accompanying claims. 

1. A multi-chip package comprising: a package substrate including a first surface having a plurality of bonding tips formed thereon and a second surface opposite to the first surface; two or more semiconductor chips vertically mounted on the package substrate, at least one of the chips including: a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern disposed over at least a portion of the peripheral circuit region; a passivation layer covering portions of the bond pad-wiring pattern and the semiconductor substrate; a pad-rearrangement pattern contacting the bond pad-wiring pattern, the pad-rearrangement pattern including a bond pad disposed over at least a portion of the cell region; an insulating layer disposed on the pad-rearrangement pattern; and a bonding wire electrically connected between the bonding tip and the bond pad, wherein a portion of the bond pad is exposed through the insulating layer.
 2. The multi-chip package of claim 1, further comprising an interlayer dielectric disposed between the passivation layer and the pad-rearrangement pattern.
 3. The multi-chip package of claim 2, wherein the interlayer dielectric comprises at least two different dielectrics.
 4. The multi-chip package of claim 3, wherein one of the two different dielectrics comprises an oxide.
 5. The multi-chip package of claim 3, wherein one of the two different dielectrics comprises a material selected from the group consisting of BCB, PBO and polyimide.
 6. The multi-chip package of claim 1, wherein the two or more semiconductor chips are only mounted on the first surface of the package substrate.
 7. The multi-chip package of claim 6, wherein an upper chip is electrically coupled to a lower chip.
 8. The multi-chip package of claim 1, wherein the pad-rearrangement pattern comprises at least two conductive layers.
 9. The multi-chip of claim 8, wherein one of the two conductive layers comprises copper.
 10. The multi-chip package of claim 1, further comprising solder balls disposed on the second surface of the substrate.
 11. The multi-chip package of claim 10, further comprising an encapsulant covering a portion of the first surface of the package substrate and the two or more semiconductor chips.
 12. The multi-chip package of claim 11, wherein a portion of the bonding tip penetrates the package substrate from the first surface to the second surface of the package substrate.
 13. A multi-chip package comprising: a lead frame; and two or more semiconductor chips electrically connected to the lead frame, at least one of the chips including: a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern disposed over at least a portion of the peripheral circuit region; a passivation layer covering portions of the bond pad-wiring pattern and the semiconductor substrate; a pad-rearrangement pattern connected to the bond pad-wiring pattern, the pad-rearrangement pattern including a bond pad disposed over at least a portion of the cell region; an insulating layer disposed on the pad-rearrangement pattern, the insulating layer having an opening to expose at least a portion of the bond pad; and a bonding wire electrically connected between the lead frame and the bond pad.
 14. The multi-chip package of claim 13, further comprising an interlayer dielectric disposed between the passivation layer and the pad-rearrangement pattern.
 15. The multi-chip package of claim 14, wherein the interlayer dielectric comprises at least two different dielectrics.
 16. The multi-chip package of claim 13, wherein the two or more semiconductor chips are vertically stacked on the lead frame.
 17. The multi-chip package of claim 16, wherein an upper chip is electrically coupled to a lower chip.
 18. The multi-chip package of claim 13, wherein the lead frame comprising a die pad including a first side and a second side opposite to the first side, and wherein at least one of the semiconductor chips is attached to the first side of the die pad.
 19. The multi-chip package of claim 18, wherein another semiconductor chip is attached to the second side of the die pad.
 20. The multi-chip package of claim 13, wherein the bond pad-wiring pattern is disposed substantially in a center region of the semiconductor substrate.
 21. The multi-chip package of claim 1, wherein the cell region is a region for memory elements and the peripheral circuit region is not a region for memory elements.
 22. The multi-chip package of claim 1, wherein the bond pad is adjacent to one side of the semiconductor substrate.
 23. The multi-chip package of claim 13, wherein the cell region is a region for memory elements and the peripheral circuit region is not a region for memory elements.
 24. The multi-chip package of claim 13, wherein the bond pad is adjacent to one side of the semiconductor substrate. 